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FAQ: How are differential pairs handled in Xilinx Devices?

Filed under FAQ / JTAG IEEE 1149.1

Q: How are differential pairs handled in Xilinx Devices?

Answer:

When you specify a pin as a differential on Xilinx Devices, the scan cells on the N side get disconnected from the I/O and all differential traffic is monitored from the P side scan cells. The N-Side scan cells are still present, and you can still see the N side scan cells (and put values in them), but they don't perform anything.

All this applies to post configuration. With Pre-configuration you have a total control over all scan cells.
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